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fix(bench): grade cache and branch behaviour on Cachegrind simulation - #233
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The zero-regression gate graded hardware cache-references, cache-misses and branch-misses against the 5% median budget, but on a shared machine those counters move by more than the budget between runs of identical code: cartesian measured +4.6% cache-references against itself, with a per-side IQR of 11-17% of the median, and failed the full gate at +5.5% while a rerun of the same comparison measured +3.5%. Each case now also runs once per side under Cachegrind with cache and branch simulation and address randomisation off. Simulated instructions, L1 misses, last-level misses and branch mispredictions are graded against the same 5% budget; two runs of one binary agree to within one count. Wall time, hardware instructions, allocations, semantic checks and the pass rule are unchanged, and the hardware cache and branch counters stay in the report for diagnosis. Closes #232
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Closes #232. Smoke run (cartesian, v0.24.0 baseline): sim instructions -1.3%, L1 misses -10.2%, LL misses -0.7%, branch mispredicts -8.4%; hardware cache/branch counters reported only.