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fix(bench): grade cache and branch behaviour on layout-stable counters - #240
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Cachegrind's simulated caches and branch predictor repeat exactly for one binary but index by code address, so they move when the linker places functions differently, and placement follows symbol hashes. Rebuilding v0.25.1 with only -C metadata changed moved list_change's simulated branch mispredictions by +6.8% with identical instructions; across ten such layouts simulated instruction-L1 misses moved by up to 133% and indirect mispredictions by up to 475%, and an edit inside one function turned 970 indirect mispredictions into 859k with equal instruction counts, while the hardware branch-misses counter on the same runs moved under 0.1%. Each side is now built in SIM_LAYOUTS (default 5) layouts that differ only in -C metadata, and each simulated metric is taken as its median across them (layout 0 is the timed binary; every layout's count is reported). Simulated instructions, data-L1 misses and last-level misses, stable across layouts, are graded on the unchanged 5% budget. Simulated instruction-L1 misses and branch mispredictions become report-only, and branch behaviour is graded on the hardware branch-misses median instead (baseline interquartile range 0.04-2.2% on the isolated CPU). Simulations run SIM_JOBS at a time before the timed trials; simulated counts do not depend on load. Closes #239
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Closes #239.
Evidence:
Budget (5%), pass rule, exact allocation checks, wall and instruction grading unchanged.