Skip to content

WIP macb stall patches #7667

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Draft
nbuchwitz wants to merge 5 commits into
base: rpi-6.18.y
Choose a base branch
from
Draft

WIP macb stall patches #7667

Changes from all commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
c9aa1a5
net: macb: schedule TX NAPI on timeout for lost completions
nbuchwitz Sep 30, 2026
4960baf
net: macb: credit unsent frames to BQL in macb_tx_error_task()
nbuchwitz Sep 30, 2026
d9a828b
net: macb: flush the IER write before re-checking the ring
nbuchwitz Oct 18, 2026
3f8a93c
net: macb: reprogram TBQP after shuffling the TX ring on link-up
chrta-wmi Oct 22, 2026
8e98fa6
net: macb: kick the transmitter on link-up
sdirkwinkel Oct 23, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
48 changes: 44 additions & 4 deletions drivers/net/ethernet/cadence/macb_main.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -854,7 +854,7 @@ static void gem_shuffle_tx_one_ring(struct macb_queue *queue)
if (!count) {
queue->tx_head = 0;
queue->tx_tail = 0;
goto unlock;
goto reset_hw_ptr;
}

shift = tail % ring_size;
Expand Down Expand Up @@ -903,6 +903,13 @@ static void gem_shuffle_tx_one_ring(struct macb_queue *queue)
/* Make descriptor updates visible to hardware */
wmb();

reset_hw_ptr:
/* tx_tail was reset to the ring base, so TBQP must be reprogrammed
* to match; otherwise it keeps pointing at a stale descriptor. Safe
* to write directly here as TX is still disabled (called from
* macb_mac_link_up() before TE is set).
*/
queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
unlock:
spin_unlock_irqrestore(&queue->tx_ptr_lock, flags);
}
Expand All @@ -917,6 +924,8 @@ static void gem_shuffle_tx_rings(struct macb *bp)
gem_shuffle_tx_one_ring(queue);
}

static void macb_tx_restart(struct macb_queue *queue);

static void macb_mac_link_up(struct phylink_config *config,
struct phy_device *phy,
unsigned int mode, phy_interface_t interface,
Expand Down Expand Up @@ -980,6 +989,12 @@ static void macb_mac_link_up(struct phylink_config *config,

macb_writel(bp, NCR, ctrl | MACB_BIT(RE) | MACB_BIT(TE));

if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
/* With BQL holding a queue stopped no xmit would issue TSTART */
for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
macb_tx_restart(queue);
}

netif_tx_wake_all_queues(ndev);
}

Expand Down Expand Up @@ -1357,10 +1372,8 @@ static void macb_tx_error_task(struct work_struct *work)
skb->data);
bp->dev->stats.tx_packets++;
queue->stats.tx_packets++;
packets++;
bp->dev->stats.tx_bytes += skb->len;
queue->stats.tx_bytes += skb->len;
bytes += skb->len;
}
} else {
/* "Buffers exhausted mid-frame" errors may only happen
Expand All @@ -1374,6 +1387,12 @@ static void macb_tx_error_task(struct work_struct *work)
desc->ctrl = ctrl | MACB_BIT(TX_USED);
}

/* BQL has to see every frame leaving the ring, sent or not */
if (skb) {
packets++;
bytes += skb->len;
}

macb_tx_unmap(bp, tx_skb, 0);
}

Expand Down Expand Up @@ -1917,7 +1936,11 @@ static int macb_rx_poll(struct napi_struct *napi, int budget)
* potentially race with the interrupt handler doing the same
* actions if an interrupt is raised just after enabling them,
* but this should be harmless.
*
* The IER write is posted. Flush it before checking the ring,
* a completion in between would raise no interrupt.
*/
queue_readl(queue, IMR);
if (macb_rx_pending(queue)) {
queue_writel(queue, IDR, bp->rx_intr_mask);
if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
Expand Down Expand Up @@ -2012,7 +2035,11 @@ static int macb_tx_poll(struct napi_struct *napi, int budget)
* potentially race with the interrupt handler doing the same
* actions if an interrupt is raised just after enabling them,
* but this should be harmless.
*
* The IER write is posted. Flush it before checking the ring,
* a completion in between would raise no interrupt.
*/
queue_readl(queue, IMR);
if (macb_tx_complete_pending(queue)) {
queue_writel(queue, IDR, MACB_BIT(TCOMP));
if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
Expand Down Expand Up @@ -4709,8 +4736,21 @@ static int macb_setup_tc(struct net_device *dev, enum tc_setup_type type,
static void macb_tx_timeout(struct net_device *dev, unsigned int q)
{
struct macb *bp = netdev_priv(dev);
struct macb_queue *queue = &bp->queues[q];

macb_tx_restart(&bp->queues[q]);
macb_tx_restart(queue);

/* The frames may have gone out with their TCOMP interrupt lost.
* macb_tx_restart() does nothing then as TBQP already matches
* tx_head, so run TX NAPI to complete them or the queue stays
* stopped.
*/
if (macb_tx_complete_pending(queue)) {
queue_writel(queue, IDR, MACB_BIT(TCOMP));
if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
queue_writel(queue, ISR, MACB_BIT(TCOMP));
napi_schedule(&queue->napi_tx);
}
}

static const struct net_device_ops macb_netdev_ops = {
Expand Down
Loading