The RISC-V Virtual Machine
An x86/x64 instruction disassembler written in C
PasRISCV is a RV64GCV/RVA23 RISC-V emulator, which is implemented in Object Pascal
Memory Engine and Scanner for iOS/MacOS using Mach API
RISC-V emulator/simulator in Python
The PasVulkan-based emulator frontend for the PasRISCV RV64GC RISC-V emulator
Exhaustive differential validation of all 4.3B AArch64 instruction encodings.
CPU emulator featuring a custom instruction set, two-pass assembler, interactive debugger, interrupts, privilege modes, virtual peripherals, and preemptive multitasking.
A simulation of a Simple-As-Possible (SAP) computer, implemented in Logisim Evolution.
🍎🪨📜🔍 Run RISC-V Linux programs on arm64: Apple silicon Macs and arm64 Linux hosts. RV64GC plus the RVA23 userland extensions (Zba/Zbb/Zbs/Zicond, Zfhmin/Zfa, experimental RVV subset). A Rosetta 2-style user-mode JIT translator — Direct mode (rvrun), riscv64 containers in a lightweight Linux VM, or binfmt_misc.
a web based front end only helper tool that provides Instruction Decoder and Converter in hexadecimal binary decimal form encoding of different ISA
A hardware implementation of a MIPS processor written in VHDL
ARMv7-M (Thumb) instruction decoder and disassembler in Python - full instruction set, objdump-compatible output, generated from a YAML spec.
A Java-based MIPS disassembler that converts binary machine code into readable MIPS assembly instructions, supporting key R- and I-format instructions with branch target address resolution.
To associate your repository with the instruction-decoding topic, visit your repo's landing page and select "manage topics."