A high-performance C++20 cache simulator with power/area modeling, MESI coherence, prefetching, and multi-level hierarchy support for architecture research and education.
A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement, multi-mode simulations, and comprehensive testing strategies for optimized processor performance.
A UVM-based verification environment for a multi-core, write-back L2 cache on 32-bit RISC-V, enforcing MESI coherence with L1 caches and interfacing to DRAM over AXI4-Lite.
Murphi code of MESI w/ Self-degradation & support for arbitrary network reordering.
A C-based multicore processor simulator with a 5-stage pipeline, direct-mapped caches, and MESI bus-coherence protocol. Simulates parallel execution and memory synchronization across 4 cores.
Multi-core CPU cache hierarchy simulator in C++20 — L1/L2/L3 with MESI coherency, LRU/FIFO/Random eviction, false sharing demo, trace-driven mode. 27 tests.
Project about cache coherence using the MESI protocol. It is for the Computer Organization and Architecture II subject on CEFET-MG.
Trabalho prático de implementação em ARQ II: Desenvolvimento de um simulador de coerência de cache utilizando a extensão do protocolo MESI, o MESIF.
Computer Architecture Course Project. MESI Protocol Simulator UI.
MESI Cache Coherency Protocol Simulator - Trabalho para a Disciplina de Arquitetura e Organização de Computadores II
RTL implementation of a quad-core MESI cache coherence protocol using SystemVerilog. The design models four processor caches connected through a shared bus.
Hardware-Conscious Performance Engineering: AVX2 SIMD, Cache Tiling, Loop Unrolling for 2D Convolutions & SGEMM injected into llama.cpp (CS 683, IIT Bombay)
Introduction to cache coherence: false sharing, MESI protocol and vectorization
Cache coherence verification: exhaustive MESI protocol model checking, a 4-core snoopy RTL cluster, litmus tests judged against an exhaustive sequential-consistency oracle, and mutation-qualified checkers.
Laboratory for the Multiprocessor Structures course @ ACS, UPB 2020
MESI Cache Coherence Simulator for Multicore Systems
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